Making a Standalone ADC | PCM Modulator

Hello there!!!

Though there are many already available ICs and loads of content on how to make your own ADC, there's a little problem... almost all of those projects INTERFACE an ADC IC with a micro processor or uP which was not desirable for the application of the ADC that I was looking for; also some were using ICs which were not easily available in the market.

So after some research and brain storming I designed a circuit which gives a descent output whose complete designing I will be sharing with you all in this blog.

Also, this is my VERY FIRST BLOG!!!... wish me luck🙂

THEORY:

PCM or Pulse Code Modulation is a Digital Modulation Scheme in which the Analog voltages are represented in digital form, i.e in 1s and 0s, for this we basically need 3 things viz. SAMPLER, QUANTIZER and ENCODER.

These exact 3 things are readily available inside an ADC IC!... so we will be using a very common ADC IC 0808 for that, however the output of this IC is Parallel but PCM is transmitted over single channel!!…. so we are using a Parallel to Serial converter(or PISO) IC 74LS165 to achieve the same.

Also we would be using two NE555 timers in astable mode to generate clock signals for ADC and PISO respectively, and lastly we are using a NOT GATE or 74LS04 for "interfacing" of the two main ICs ADC and PISO.

CIRCUIT SPECIFICATIONS:

1. TITLE: PCM Modulator
2. RESOLUTION:  8 Bits
3. OUTPUT FREQUENCY:  Typically 1.23kHz
4. OUTPUT TYPE:  Serial
5. WORKING VOLTAGE:  5V DC
6. ADDITIONAL FEATURE:  Synchronous pulse available for demodulation

COMPONENTS NEEDED:

1. ADC 0808:  8 channel Successive Approximation ADC
2. 74LS04:  Hex Inverter
3. 74LS165:  Parallel-In-Serial-Out Shift Register
4. NE555:  Timer IC
5. SPDT Switch
6. Capacitors
7. Resistors

CIRCUIT & ITS WORKING:

Circuit Design in Proteus

The Clamper circuit

Any input to an ADC usually varies between its Ground and VCC potentials, meaning you cannot give a negative voltage as input to it.

So, one cannot simply give an AC signal as input, as the signal varies between +V and -V; hence we are using a POSITIVE UNBIASED CLAMPER which clamps the input AC signal to a positive voltage V so that now the signal varies between 0V and +2V.

SPDT Switch

An input to a clamper circuit can ONLY be AC but not DC, so both AC and DC signals must be given separately to the input pin of ADC and hence we are using an SPDT or Single Pole Double Throw switch at the input side.                                                   

The ADC Connections

The three address lines PIN 23,24 & 25 are tied to ground as we are giving input to only one pin i.e. INT 0 (PIN 26).

Vref + and Vref - pins are tied to 5V and GND respectively as we want full and linear scaling of the ADC, to know more about this you can learn about "Differential Input ADCs".

The START and EOC(or End of Conversion) pins are tied together to make the ADC STANDALONE, which means it DOESN'T require any microcontroller/processor to send an activating pulse at the START pin; our circuit does these things by itself!

The PIN 10 is given clock signal which is basically a square wave of almost 50% duty cycle.

The rest other pins are connected in such a way that the output is always available at the 8 output pins, refer the datasheet for more information.

The Shift register or PISO

The 8 bits output of the ADC are connected at the 8 input terminals of the shift register according to the bit significance, i.e. MSB and LSB are taken care of while connection.

PIN 1 is like the control pin, when its low the data is loaded in the internal registers and when its high the 8 bits are RIGHT SHIFTED and sent to the output pin, this right shifting operation is the actual "parallel to serial" conversion. Its given the negation of EOC/START and the reason is discussed in the next section.

PIN 10 or SERIAL INPUT pin is grounded. When all the 8 bits are shifted and the IC is still in right shifting mode, then the input at PIN 10 is directly sent to the output, now as its grounded a logic 0 will be sent at the output after shifting 8 bits.

PIN 2 is given clock signal, which in our case is different from the clock of the ADC.
PIN 15 or Clock Inhibit pin is grounded, its usually used for advanced applications; again, refer the datasheet for more information.

Why NOT gate?

The SH/LD' of PISO is given the negation of START/EOC of the ADC which is necessary for the combined working/interfacing of both the ICs.

From this connection, we are ensuring two main things, viz. :

1. The PISO will be right shifting the PREVIOSLY available data at its input, meanwhile the ADC is converting the CURRENT analog input into 8 binary bits.
2. The PISO will stop the shifting and load the new 8 bit data into its internal registers when the ADC has done completing the conversion of new analog input.

Do refer the function and timing diagrams of the pins involved for better and deeper understanding from the datasheet.

Why two different clocks?

When both the ICs are given the same clock, then the PCM output data becomes discontinuous i.e. after 8 bit PCM data we get a 0V at the output(as SI pin of PISO is grounded); this means that the PISO is working faster when compared to ADC in this case.

PCM output with same clocks

The first one is the DC input, second one is SYNC PULSE and the last one is PCM output.

So for getting a continuous PCM data, a SLOWER clock is given to the PISO when compared to that of ADC. When proper clock is selected for PISO with respect to ADC, we get the following DESIRED output:

Desired PCM output

Clock selection

The ADC is given a clock of 10kHz, as it is the minimum possible clock of the ADC according to the datasheet.

For calculating the clock of PISO, first I calculated the time the ADC is taking for converting one sample of analog value by calculating the time period of the EOC pulse.

Conversion time calculation using EOC

Now we have to design the clock in such a way that the 8 PCM bits lie in this EOC time period, to do that I did some simple math and arrived at a clock frequency of 1.23kHz. Remember that the shift register shifts the bit to right at every trailing edge of the clock.

PISO clock calculation

For generating clock, I have used NE555 timer IC in astable mode whose design is quiet simple and can be easily found in any book or on the internet. I have designed it for 67% duty cycle which is minimum possible duty cycle for a normal 555IC circuit.

SCOPE FOR IMPROVMENTS:

Instead of using two 555 timer ICs to generate 2 clocks, it is advisable to use only one 555 IC timer for generating 10kHz signal and slower clock can be generated using a simple frequency divider circuit.

Before giving the input directly to the ADC, a SAMPLE & HOLD circuit may be placed which will hold the sample of analog input till the conversion time of ADC for stabilized input resulting in better output.

Instead of using a normal 555IC timer circuit, one can always go for another configuration(i.e. circuit) of 555IC circuit which gives a clock at almost 50% duty cycle, for example using a diode to bypass Rb resistor.

RESULT & CONCLUSION:

I was getting a descent output with little fluctuations/ disturbances on the breadboard. The slight disturbances were due to the use to many long jumpers in the circuit.
If you want to get even better output, I suggest you to make a SPECIAL PURPOSE  PCB for the circuit.

So these were the complete details of my project, I have tried my level best to make you understand everything in a simple and easy manner.

Hope you guys have enjoyed it! Feel free to ask any doubts in the comments below, I will try to address them, also I'm open to suggestions! If you have got any feedback for me, tell me in the comments.

Adios Amigos!!!